ChimeraTK-DeviceAccess
03.18.00
pcieuni_io_compat.h
Go to the documentation of this file.
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// SPDX-FileCopyrightText: Deutsches Elektronen-Synchrotron DESY, MSK, ChimeraTK Project <chimeratk-support@desy.de>
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// SPDX-License-Identifier: LGPL-3.0-or-later
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#pragma once
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// This is C code from the kernel driver. Turn off the C++ linter warnings
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// NOLINTBEGIN
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#include <sys/types.h>
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static
const
loff_t PCIEUNI_BAR_OFFSETS[6] = {0LL, (1LL) << 60, (2LL) << 60, (3LL) << 60, (4LL) << 60, (5LL) << 60};
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typedef
struct
_pcieuni_ioctl_bar_sizes
{
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size_t
barSizes
[6];
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size_t
dmaAreaSize
;
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}
pcieuni_ioctl_bar_sizes
;
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/* Use 'U' like pcieUni as magic number */
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#define PCIEUNI_IOC 'U'
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/* relative to the new IOC we keep the same ioctls */
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#define PCIEUNI_PHYSICAL_SLOT _IOWR(PCIEUNI_IOC, 60, int)
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#define PCIEUNI_DRIVER_VERSION _IOWR(PCIEUNI_IOC, 61, int)
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#define PCIEUNI_FIRMWARE_VERSION _IOWR(PCIEUNI_IOC, 62, int)
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#define PCIEUNI_GET_DMA_TIME _IOWR(PCIEUNI_IOC, 70, int)
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#define PCIEUNI_WRITE_DMA _IOWR(PCIEUNI_IOC, 71, int)
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#define PCIEUNI_READ_DMA _IOWR(PCIEUNI_IOC, 72, int)
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#define PCIEUNI_SET_IRQ _IOWR(PCIEUNI_IOC, 73, int)
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#define PCIEUNI_IOC_MINNR 60
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#define PCIEUNI_IOC_MAXNR 63
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#define PCIEUNI_IOC_DMA_MINNR 70
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#define PCIEUNI_IOC_DMA_MAXNR 74
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// NOLINTEND
_pcieuni_ioctl_bar_sizes::barSizes
size_t barSizes[6]
Definition:
pcieuni_io_compat.h:18
_pcieuni_ioctl_bar_sizes::dmaAreaSize
size_t dmaAreaSize
Sizes of bar 0 to 5.
Definition:
pcieuni_io_compat.h:19
pcieuni_ioctl_bar_sizes
struct _pcieuni_ioctl_bar_sizes pcieuni_ioctl_bar_sizes
Information about the bar sizes.
_pcieuni_ioctl_bar_sizes
Information about the bar sizes.
Definition:
pcieuni_io_compat.h:17
sources
ChimeraTK-DeviceAccess
backends
pcie
include
pcieuni_io_compat.h
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